Japanese Patent Application No. 2001-143634, filed on May 14, 2001, is hereby incorporated by reference in its entirety.
The present invention relates to a signal reception circuit, and a data transfer control device and electronic equipment using the same.
The Universal Serial Bus (USB) standard has recently attracted attention as an interface standard for connections between personal computers and peripheral equipment (broadly speaking: electronic equipment). This USB standard has the advantage of enabling the use of connectors of the same standard to connect peripheral equipment such as a mouse, keyboard, and printer, which are connected by connectors of different standards in the prior art, and of making it possible to implement plug-and-play and hot-plug features.
In comparison with the IEEE 1394 standard, which is also attracting notice as a standard for the same serial bus interface, this USB standard has a problem in that the transfer speed thereof is slower.
Under such circumstances, attention is focussed on the establishment of the USB 2.0 standard which can implement a data transfer speed of 480 Mbps (in high speed (HS) mode), far faster than that of the previous USB 1.1 standard, while maintaining backward compatibility with USB 1.1. The USB 2.0 transceiver macrocell interface (UTMI) has also established in which the interface specification for a physical layer circuit and a logical layer circuit according to the USB 2.0 standard are defined.
According to one aspect of the present invention, there is provided a signal reception circuit for receiving a differential pair of input signals, comprising:
first and second reception circuits which receive a differential pair of input signals to generate first and second reception signals;
a first signal detection circuit which detects the differential pair of input signals based on a first reference level, in a first mode for high speed; and
a second signal detection circuit which detects the differential pair of input signals based on a second reference level which is higher than the first reference level, in a second mode for low speed,
wherein the first reception signal is enabled when the differential pair of input signals is detected by the first signal detection circuit; and
wherein the second reception signal is enabled when the differential pair of input signals is detected by the second signal detection circuit.